In general, when forming a Complementary Metal Oxide Semiconductor (CMOS) in which an n channel type MOS transistor and a p channel MOS transistor are integrated on the same substrate, gate patterns and a silicide are formed. Then, to fill a space between the gate patterns, an insulating layer is formed using a Boron Phospho Silicate Glass (BPSG) oxide layer, having excellent flowability.
To suppress the diffusion of boron B in the BPSG oxide layer into a substrate during a subsequent thermal process, a pre metal dielectric (PMD) liner is formed prior to a deposition of the BPSG oxide layer.
FIG. 1 is a cross-sectional view showing a semiconductor device having a general pre metal dielectric liner.
With reference to FIG. 1, a device isolation layer 102 defines an active region of a semiconductor substrate 100 having first region A and second region B.
An n-channel type transistor is arranged in the first region A of the semiconductor device 100, and a p-channel type transistor is arranged in the second region B of the semiconductor device 100.
Further, a nitride layer 110 is arranged over an entire surface of the substrate as the PMD liner, and the BPSG oxide layer 120 is formed over the nitride layer 110.
The nitride layer 110 serves as an etch stop layer during a subsequent etching for a contact. Simultaneously, nitride layer 110 functions to suppress the diffusion of boron B in the BPSG oxide layer 120 into the semiconductor substrate 100 during a subsequent thermal treatment. When an impurity ion such as the boron B penetrates the semiconductor substrate 100, the threshold voltage of a device is locally changed, which degrades the stability of the device. In the related art, in order to suppress the penetration of the boron B to the highest degree, a gas atmosphere is controlled to increase the bonding strength of nitrogen-hydrogen N—H during the formation of the nitride layer 110. However, using only the method according to the related art, the suppression of boron B penetration into the semiconductor substrate 100 is limited. Moreover, it requires a thick nitride layer 110 as the PMD liner.